(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices and packages, and more specifically to a method used to protect the copper interconnects and low dielectric constant (low k) materials of the semiconductor device during subsequent dicing, interconnection processes and further packaging procedures.
(2) Description of Prior Art
To increase semiconductor device performance or to decrease resistance—capacitances (RC) delay the semiconductor industry has been employing copper as an interconnect material replacing more resistant aluminum based structures, while employing dielectric layers with a lower dielectric constant than silicon oxide to replace higher dielectric constant materials. The presence of low k layers, resulting in decreased capacitance, however inherently presents lower mechanical and thermal stability than the higher k, silicon oxide layers. Therefore low k layers present in semiconductor devices can present yield as well as reliability vulnerabilities in terms of interfacial delamination and cracking which can occur in the low k layers as a result of subsequent semiconductor device or packing procedures. For example the flip chip process of connecting solder balls or bumps of a semiconductor chip to an underlying package, as well as the dicing procedure used to separate individual semiconductor chips from a completed semiconductor substrate, can result in undesirable phenomena such as adhesion losses between copper and the low k layer, as well as micro-cracking of these same materials. To enhance the mechanical strength of these materials undoped silica glass (USG) layers have been formed on the underlying low k layers and copper interconnect structures allowing these structures to more adequately survive subsequent processing procedures, however the presence of the higher k, USG layers increase parasitic capacitance thus reducing the performance benefit derived with the use of low k layers.
The present invention will offer materials and a process sequence in which the performance benefit of low k layers and copper interconnect structures is not compromised via the presence of overlying higher k dielectric layers, while the mechanical vulnerabilities of the low k and copper interconnect structures are not adversely influenced during subsequent process steps such as formation of redistribution layers (RDL) for the solder bumps, formation of solder bumps, or the dicing procedure. Prior art such as Yu et al in U.S. Pat. No. 6,187,663 B1, as well as Chang et al in U.S. Pat. No. 6,281,115 B1, describe methods of fabricating semiconductor devices comprised with low k layers and copper interconnect structures, however these prior art do not describe the process sequence or materials described in the present invention in which the low k layers and copper interconnect structures are protected by low k polymer encapsulation during pre-dicing as well as during dicing procedures.